D4T Systems provides the customer with a fully integrated test automation tool. Our tools are uniquely positioned to tackle test during the design phase in the IC product creation process, while maintaining interaction with the standard analog design environment. In addition, our tools enable the link to the standard procedures in the test program engineering running at various ATE platforms, thereby enabling smooth and flawless  test development flow. The methodology bridges the gap and connects the design and test community in the analog IC design world.
Overall, our solutions add value to customers in the reduction of test cost, while increasing the quality and accelerating the time-to-market, all achieved by:

•  Full analog test solution from the test specification at the IP level to the System level towards the Tester platform.
• Integrating and validating analog test during design cycle.
• Up and running test plan before silicon tape-out

The test approach for mixed signal circuits is based on creating the test benches early in the design phase. By integrating the test automation into the design flow, D4T offers a highly flexible approach in which the test plan can be verified and validated at pre-silicon.  This dramatically reduces the time needed to implement a mixed signal test bench. Moreover, since the test implementation is integrated into the design, the test plan can be verified and reduces the risk of having an invalid implementation on silicon.
 

Closing the loop in AMS testing

We define a closing loop in mixed signal testing. D4T automation tools are positioned between design environment and tester platform. In many cases AMS chip development will consist of different IP (either digital, mixed signal or fully analog) for which a test infrastructure is defined. This infrastructure is controlled by a test interface (i.e. IEEE1149 JTAG) and provides the required access to the different IP blocks on the chip. Next, the tester platform (i.e Verigy) which reads and writes data and analog signals to and from the chip must be incorporated in the test flow. D4T test tools are capable of interpreting this test infrastructure and the IP behavior and can run a simulation in the Integrated Design Environment. The system level implementation of the test architecture can now effectively be verified.

Test automation process

The test cost reduction and quality increase are achieved using our original tools, as offered in the test automation package. The tools offer automatic test bench generation based on the test specification, as well as interfacing to a number of tester platforms (e.g. Verigy, Teradyne).

The test bench is generated starting from the test specification of the IP, usually provided by the designer of the block. Our tools perform the test spec analysis and generate the testbench of the IP with test stimuli/responses. This testbench is generated in two formats:

• Simulator format, readable by any of the standard EDA simulators (Spectre, NcSim.AMS), to validate the approach by simulation at the arbitrary level of circuit abstraction.
• ATE format, to transfer the test signals towards the back-end test engineering process and linking it to different test platforms.

The design hierarchy, when the IP is a part of the more complex systems-on-chips, is also addressed, allowing the transfer of the test-bench in both formats to the system-level, incorporating the top-level test spec to the test-bench generation at the top-level. Once the user is satisfied with the test bench and has optimized his test stimuli, D4T tools can output the correct language format for the tester platform. In such a way, the entire test development process becomes fully integrated in the design process, bridging the gap between design and test engineers and closing the loop in the AMS testing.